February 14 - 16, 2006

Salient areas covered in the workshop

• Digital Design Objective
• Clock Methodology, Critical & Cycle Time
• Verilog HDL Basics, Abstraction Levels
• Module Basics, Module Instances
• Hierarchal Design
• IGate Level Modeling
• Data-Flow: Continuous Assignments
• Operators
• Behavioral Modeling
• Procedural Blocks (initial, always)
• Blocking & Non-Blocking Assignments
• Clock & Async/Sync Reset in Digital System
• Built-in-Self Test (BIST) in chips
• Boundary Scan Testing
• Digital Systems, State Machine Concept
• RTL Coding Guidelines
• Introduction of FPGA
• Xilinx FPGA Basics
• Xilinx FPGA CLBs
• LUT Implementation in CLBs, FPGA I/O Blocks
• Xilinx XC4000 and Spartan Series FPGA internal architecture
• Xilinx FPGA Design Process
• Core Generator
• Synthesis & Implementation, Configuration Flow
• Timing Simulation with ModelSim & ISE 6.1i